1. Field of the Invention
This invention relates to test techniques for high-bandwidth circuits and, more particularly, to tuning of test traces that are capacitively coupled to signal traces.
2. Description of the Related Art
High-bandwidth interconnects, such as serializer/deserializer (serdes) interconnects, are becoming increasingly common in the design of computing systems. For example, serdes interconnects may be used in place of parallel interconnects to reduce interconnect pin count while preserving high rates of data transfer. Such interconnects may be employed to interface distinct portions of a single system component, such as a single integrated circuit, or to interface different components within a system, such as peripherals, processors, memory devices or other types of components.
As high-bandwidth interconnects proliferate, it is increasingly important to ensure that such interconnects operate reliably in the face of many possible failure modes, such as may be induced by component manufacturing defects, system assembly flaws, or operational failures. One aspect of reliability assurance includes providing an effective test methodology for detecting interconnect faults. However, owing to the sensitivity of many high-bandwidth interconnect designs, testing of such interconnects may need to be minimally invasive in order to avoid perturbing the normal operating characteristics of the interconnect. In turn, minimally invasive test techniques may be particularly susceptible to noise, making it especially difficult to design a test methodology that is reliable in detecting faults and minimally degrades the normal operating performance of the interconnects being tested.